1. Field of the Invention
This invention relates generally to the manufacture of semiconductor wafers and more specifically, this invention relates to a method of reworking semiconductor wafers that have a faulty metal layer deposition process or a faulty metal layer etch process.
2. Discussion of the Related Art
The processes related to the deposition and etching of metal layers that are used for forming interconnections are at the backend of the semiconductor fabrication process and, as can be appreciated, the semiconductor wafers have almost reached their maximum value. As can be further appreciated, if the very last process fails, the entire wafer must be scrapped with the concomitant loss of the value of the wafer.
FIG. 1 is a flow diagram of the prior art method of manufacturing semiconductor wafers. The method of manufacturing semiconductor devices on semiconductor wafers starts as shown at 100. As is known in the semiconductor art, after a wafer is completely processed, the wafer is "diced," that is, cut into many chips. The future chips on the wafer are subjected to a series of processes as shown at 102 including forming active elements in a semiconductor substrate and forming a layer of an interlayer dielectric on the surface of the semiconductor substrate. As is known in the semiconductor manufacturing art, at least one metal layer is formed on the surface of the interlayer dielectric as shown at 104. The metal layer is etched to form electrical interconnects either between one portion of the semiconductor and including connections by vias to a layer underlying the metal layer or to a layer overlying the metal layer. The metal layer is also known as a metal stack because it is typically formed from several different layers of materials. For example, a first layer of material could be a barrier layer made of TiW/Ti, the next layer of material could be a layer of aluminum, the next layer of material could be an anti-reflective coating, typically, Ti/TiN and the last layer could be a hard mask layer made of TEOS. All of these materials are well known in the semiconductor manufacturing art as is the method of depositing them and will not be further discussed.
After the metal layer is formed at 104, the metal layer is checked at 106 before the wafer is sent to the next process. If the metal layer is not good, the wafer is scrapped as shown at 108. If the metal layer is good, the metal layer is etched, at 110. The quality of the metal etch is checked at 112 and if not good, the wafer is scrapped at 108. If the metal layer etch is good, it is determined at 114 if the metal process just completed is the last metal process and if not, the wafer is further processed as shown at 116. If the metal process just completed is the last metal process, the wafer is processed to completion, as shown at 118.
The processing of a semiconductor wafer is becoming more and more process intensive, that is, there are many more processes being incorporated into the overall manufacturing process as the wafers become more complex and as more metal layers become necessary. The amount of time and expense invested in each wafer increases as the overall manufacturing process nears completion, and as can be appreciated, when the last metal layer is being processed, the semiconductor wafer has almost reached its maximum value. The processes involving metal deposition and metal etching are becoming more and more critical because of the structural complexity of films used in metal depositions and the chemistry used in etching processes.
As discussed above, in the current manufacturing process, if the last metal layer fails, the wafer is scrapped with the entire investment in the wafer having to be amortized over the remaining wafers that are good. This amortization causes the price of the surviving wafers to be increased and depending upon economic forces in the marketplace, the profit margin to the semiconductor manufacturer is decreased and in some cases, there may be no profit margin at all.
Therefore, what is needed is a rework procedure to save the majority, if not all of the wafers that have faulty metal layers caused by faulty metal deposition or metal etch processes.